By James E. Smith (auth.), Pen-Chung Yew, Jingling Xue (eds.)
On behalf of this system committee, we have been happy to give this year’s application for ACSAC: Asia-Paci?c desktops structure convention. Now in its 9th yr, ACSAC maintains to supply an exceptional discussion board for researchers, educators and practitioners to return to the Asia-Paci?c quarter to switch rules at the newest advancements in computers structure. This yr, the paper submission and evaluate approaches have been semiautomated utilizing the unfastened model of CyberChair. We got 152 submissions, the most important quantity ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee individuals for evaluate. all the papers have been reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the evaluate technique. whilst reviewers claimed insufficient services, extra reviewers have been solicited. after all, we bought a complete of 594 stories (3.9 according to paper) from committee participants in addition to 248 coreviewers whose names are stated within the lawsuits. we wish to thank them all for his or her time and e?ort in delivering us with such well timed and top of the range reports, a few of them on super brief notice.
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Sector cache also is able to improve single level cache system performance in some cases, particularly if the cache is small, the line size is small or the miss penalty is small. The main drawback, cache space underutilization is also shown in . Rothman propose “sector pool” for cache space underutilization. In the design, each set of set-associative cache compose of totally s-ratio sector lists. Each list has a fix number of sectors that the number is less than the associativity. S-ratio additional pointer bits, associate with a line tag, point to the actual sector as the index of the sector list.
Similar to  describe, for a P-sectored cache we divide the address A of a memory block in four sub-strings (A3, A2, A1, A0) defined as: A0 is a log2SL bit string which SL is the sector length, A1 is a log2P bit string show which sector this block is in if it is in a cache line, A2 is a log2nS bit string which nS is the number of the cache sets, A3 consists of the remaining highest significant bits. The main cache line need store only the bits in A3. Figure 2 show tag checking of directed-mapped case.
Then we run the traces through a trace-driven cache simulator. We generate both L1 memory reference traces and L2 memory reference traces. After 20 billion instructions after system start up (the target application is configured auto-run in the simulation) we collect 200 million memory references as our L1 traces. We use 100 million references of them to warm up L1 cache and analysis the behavior of the latter 100 million. The L1 sector cache we simulated is mainly configured as below with small varieties: 16KBsize, 64B line size, 16B sector size, 4 way associ- Efficient Victim Mechanism on Sector Cache Organization 23 ate, LRU replacement algorithm and write-back approach.